(1) Field of the Invention
The present invention relates to a fixed rate delay circuit wherein pulse intervals of an input pulse sequence are successively measured and, in response to a result thereof, an output pulse sequence is produced in which each pulse is delayed at a fixed rate with respect to the immediately preceding pulse interval. The output pulse sequence can be obtained even if these measured pulse intervals are varied every moment.
(2) Description of the Prior Art
Recently, with the progress of digital techniques, a SMPTE digital time code is used as an editorial code for editing by a video tape recorder (VTR). In the process of editing video signals it is required to extract timing information from a digital information signal having a signal form such as an editorial code for which the SMPTE time code is customarily used. In the ordinary reproduction of the VTR at a fixed tape speed, clock-pulses contained in the reproduced digital information signal are spaced at equal intervals, so that it is possible to extract those clock-pulses therefrom by a conventional clock reproducing circuit.
On the other hand, in the editing of video signals by the VTR, the search of pictures by high speed reproduction and the confirmation of cuts by slow speed reproduction are required in response to the editor's demand or the contents of pictures. Also, the continuously variable speed reproduction is indispensable for the efficiency and convenience of the editing. In such a variable speed reproduction of the VTR, clock-pulses contained in the reproduced editorial codes are no longer spaced at equal intervals. Besides, in the high speed reproduction of the VTR, the tape speed is not controlled so accurately as in the ordinary speed reproduction. Also, the time code is customarily recorded in a longitudinal direction of a magnetic tape by a fixed magnetic head, so that the pulse intervals of the clock-pulses which are obtained in the high speed reproduction are fluctuated in response to the fluctuation of the tape speed. Consequently, since the pulse intervals of the reproduced clock-pulses have a difference of hundreds of times between the high speed reproduction and the slow speed reproduction, it is required to realize a clock reproduction circuit in which the faithful clock reproduction can be attained by stably and securely extracting the clock timing, even if the pulse intervals thereof are varied extensively as mentioned above.
On the other hand, regarding a type of digital information signal fitted for the editing thereof carried out by employing the digital VTR in which pulse intervals of reproduced clock-pulses are varied as mentioned above, a digital information signal of biphase modulation type, for instance, biphase space type, biphase mark type and the like, is known. In this type of digital information signal, bits of information data consisting of "1's" and "0's" are separately arranged between equally spaced clock components, and digital information is discriminated on the basis of the existence of those separately arranged information bits. The digital information signal of this type is frequently adopted for the editing of video signals, since the faithful reproduction of information can be attained, even if the reproduction of various modes, for instance, high speed, slow speed and reverse direction reproductions are carried out by the digital VTR accompanied with excessive jitters of clock timing. However, even though the digital information signal of biphase modulation type is adopted, the above-mentioned clock reproduction circuit is also required for effecting the stable and reliable reproduction of variable speed clock-pulses therefrom.
For the stable and reliable reproduction of variable speed clock-pulses such as mentioned above, it is sufficient successively to detect the pulse intervals thereof and then to produce a pulse sequence, each pulse of which is delayed at the fixed rate regarding the immediately preceding detected pulse interval in order, for the following reason.
The clock-pulses are equally spaced by nature in the ordinary state, even when other information bits are separately interposed between them. In contrast therewith, the variation of the tape speed of the VTR occurs gradually at a time duration being far longer than pulse intervals thereof. Thus each pulse of the clock pulse sequence can be extracted by gating it with a gating signal stretched between two successive pulses of the clock pulse sequence. The two successive pulses are delayed respectively at a fixed rate regarding the immediately preceding pulse intervals thereof, according to the prediction based on the immediately preceding pulse interval detected for discriminating clock pulses from the interposed other information bits.
For the above reason, a fixed rate delay circuit is indispensable for the stable and reliable reproduction of clock pulses having extensively varied pulse intervals. However, a conventional delay circuit is formed of a monostable multivibrator or a delayed pulse generator having a CR time constant for generating delayed pulses. Thus, in the conventional delay circuit, it is impossible to effect the above-mentioned fixed rate delay for varying the delay time in response to the variation of pulse intervals in the pulse sequence having extensively varied pulse intervals.
On the other hand, it is true that, in order to perform the above-mentioned fixed rate delaying, a pulse phase locked logic circuit, namely, a so-called PLL circuit has been customarily used for forming a fixed rate delayed pulse based on an average pulse interval. Also, a complicated operation circuit has been traditionally used for forming the fixed rate delayed pulse based on the immediately preceding detected pulse interval. However, these conventional fixed rate delay circuits cannot follow the extensive variation of pulse intervals as mentioned above, and besides are provided with the extremely complicated circuit configuration, so that these conventional circuits have many serious defects in practical use.